The present invention relates to semiconductor memory cells and arrays. More particularly, the present invention relates to resistive random-access memory (ReRAM) cells and arrays and to circuits and methods for preventing over-programming of ReRAM memory cells and arrays of ReRAM memory cells.
ReRAM cell programming comes with the risk of over-programming ReRAM cells to an on resistance (Ron) level, which is too low to adequately re-erase them. Programming of ReRAM cells usually starts from an erased state where the ReRAM device has a high off resistance (Roff) in about the 1-10 GOhm range and should decrease the ReRAM resistance to a lower resistance Ron state, which can ideally be in about the 100 KOhm range. The programming speed depends on the power applied to the ReRAM device (the product of voltage across and current flowing through the ReRAM device).
FIG. 1A shows a four-column portion of a row of a typical ReRAM array (shown within dashed lines 10) along with typical segment circuits used to erase and program a bit-line with push-pull ReRAM cells each having a top (“Top”) and a bottom (“Bot”) ReRAM device. The segment circuits include an n-segment (shown within dashed lines 12) and a p-segment (shown within dashed lines 14). While FIG. 1 shows the segment circuits in use with a three-transistor ReRAM cell, persons of ordinary skill in the art will appreciate that the scheme of FIG. 1 is applicable to other push-pull ReRAM cell arrangements.
The row of the array is disposed between two lines VB and GB, designated by reference numerals 16 and 18, respectively, which are sometimes referred to as complementary bit lines. A bit line BL, one for each row of the array indicated by reference numeral 20, runs in the row direction of the array. The VB and GB lines 16 and 18 n-segment circuit 12, the p-segment circuit 14, and the bit line BL 20 are all formed from interconnect metal lines on the integrated circuit containing the ReRAM array 10 and as such have a characteristic resistance associated with them. The resistance from the n-segment end of the VB line 14 through the array 10 is represented by resistor RVBN at reference numeral 22. The resistance from the n-segment end of the bitline BL line 20 through the array 10 is represented by resistor RBLN at reference numeral 24. The resistance from the n-segment end of the GB line 18 through the array 10 is represented by resistor RGBN at reference numeral 26. The resistance from the p-segment end of the VB line 14 through the array 10 is represented by resistor RVBP at reference numeral 28. The resistance from the p-segment end of the bitline BL line 20 through the array 10 is represented by resistor RBLP at reference numeral 30. The resistance from the p-segment end of the GB line 18 through the array 10 is represented by resistor RGBP at reference numeral 32.
The VB, GB and BL bit-lines 16, 18, and 20 are driven to the potential at VSS line 34 (typically 0V) by pull-down n-channel MOS devices at the n-segment side 12 of the array. Thus the VB line 16 is pulled down to the potential at the VSS line 34 by transistors 38. The GB line 18 is pulled down to the potential at the VSS line 34 by transistors 40. The BL line 20 is pulled down to the potential at the VSS line 34 by transistors 42.
The VB, GB and BL bit-lines 16, 18, and 20 are driven to the potential at VPP line 36 by pull-up p-channel MOS devices at the p-segment side 14 of the array 10, where VPP is the bit-line programming-voltage (e.g. 1.8V). Thus the VB line 16 is pulled up to the potential at the VPP line 36 by transistors 44. The GB line 18 is pulled up to the potential at the VPP line 36 by transistors 46. The BL line 20 is pulled up to the potential at the VPP line 36 by transistors 48.
Depending on the operation, erasing the ReRAM device labeled TOP or BOT or programming the TOP or BOT ReRAM device, the VB, GB and BL bit-lines 16, 18, and 20 are driven either to VSS 34 or VPP 36 from one or the other of the n-channel and p-channel sides 12 and 14. Persons of ordinary skill in the art will appreciate that FIG. 1A shows an example with four three-transistor push-pull ReRAM cells, but these lines are much longer, and can be thousands of cells wide.
FIG. 1A shows all of the n-channel and p-channel pulldown and pull-up devices as two serial-connected devices. This is necessary in embodiments where these devices are the same type as the lower voltage transistors used inside the push-pull-cells, in order to avoid BVDSS problems at 1.8V programming and erase potentials. Persons of ordinary skill in the art will appreciate that where high-voltage transistors that can withstand the VPP potential are used for transistors 38, 40, 42, 44, 46, and 48, only single transistors may be employed.
Pulldown n-channel transistors 38 are controlled by VBS0=1 at their gates if VB 16 needs to be pulled down to VSS. Pulldown n-channel transistors 40 are controlled by GBS0=1 at their gates if GB 18 needs to be pulled down to VSS. Pulldown n-channel transistors 42 are controlled by BLS0=1 at their gates if BL 20 needs to be pulled down to VSS.
Similarly, pull-up p-channel transistors 44 are controlled by VBS1_B=0 at their gates if VB 16 needs to be pulled up to VPP. Pull-up p-channel transistors 46 are controlled by GBS1_B=0 at their gates if GB 18 needs to be pulled up to VPP. Pull-up p-channel transistors 48 are controlled by BLS1_B=0 at their gates if BL 20 needs to be pulled up to VPP.
As may be seen from an examination of FIG. 1A, array 10 also includes a word line (WL) 50 for each column and n-word lines (WLN) 52 and p-word lines (WLP) 54 that are shared by adjacent columns in the particular arrangement shown in FIG. 1A. The WL, WLP, and WLN word lines 50, 52, and 54 are used in programming the individual push-pull ReRAM memory cells (one of which is shown within dashed lines 56 in FIG. 1) in the array 10.
FIG. 1B is a graph showing simulated voltages and currents encountered during programming and erasing ReRAM devices in the ReRAM cells depicted in FIG. 1A. The simulation-waveforms of FIG. 1B show voltages (top waveforms), currents (center-waveforms) and power (bottom waveforms) as a function of ReRAM resistance on the X-axis on logarithmic scale in units of KOhms ranging from 100 Ohm at the left side to 1 MOhm at the right side. The bundles of 8 waveforms reflect 8 different segment length cases from 3 to 384 clusters in width, each cluster including 96 columns which range from 3*96=288 columns to 384*96=36864 columns in width. The number of columns matches the number of cells, connected to the same bit-lines. The individual waveforms differ because of the amount of metal-resistance on bit-lines, which is directly related to segment width.
Reading from right to left, programming starts slowly after applying proper bit-line voltages and selecting proper word-lines to apply that voltage across the selected ReRAM devices. If programming starts from an erased state where the ReRAM device has a high Roff, the voltage across ReRAM (top curves) is full-rail VPP, the initial current (middle curves) is very low, and the consumed power (bottom curves) is low due to the low current. Roughly in the 1 MOhm to 100 KOhm range of this example, the increasing current causes metal-line and select-device-IR-drop to increase, and the voltage across the ReRAM device drops in tandem with increasing currents in the >10 uA range. As can be seen from FIG. 1B, power-peaks are visible in the 5-50 KOhm range. Where the power-peak appears, programming (the change of Ron) occurs very rapidly and is difficult to stop before Ron saturates after the power-peak, perhaps in the 1 KOhm range. The circuit shown in FIG. 1A can cause ReRAM devices to be programmed to an unacceptably low value of Ron.
An undesirable consequence of programming ReRAM cells to such low values of Ron is that it is difficult to later re-erase them if they need to be re-programmed. At an Ron range in the region of about 1 KOhm, it is difficult to get enough voltage to the ReRAM device at high enough currents to start the erase process.
Accordingly, a challenge is how to limit the ReRAM programming to a much higher Ron level, perhaps in the 100 KOhm range, which allows ReRAM cells to be re-erased later, if needed.